1. Field of the Invention
The present invention relates to the electronic design of integrated circuits, and more specifically to a method and apparatus for the functional verification of a target integrated circuit design.
2. Related Art
Functional verification is one of the steps in the design of many integrated circuits. Functional verification generally refers to determining whether a design (xe2x80x9ctarget designxe2x80x9d) representing an integrated circuit performs a function it is designed for. In a typical design process, a designer identifies the functions to be performed and designs a circuit using high-level languages (e.g., VHDL language well known in the relevant arts) to perform the identified functions. An example of a function may be to generate a predetermined output data corresponding to a given input data. Tools available in the industry are typically used to generate a lower-level design (e.g., at gate-level) from the design specified in a high-level language. The higher level languages are generally more understandable to a user (human-being) while the lower level languages are closer in representation to the physical implementation.
Usually, the lower level design is evaluated against input data to generate output data. A determination of the accuracy of a functional design may be made based on the output data. The manner in which input data is generated and output data is used for determination of accuracy may depend on the specific type of verification environment. For example, in an emulation environment, the target design receives input data in a xe2x80x9creal environmentxe2x80x9d usually having other components, whose operation can be relied on for accuracy. The target design is implemented to typically operate at least with these other components. By testing the target design in combination with these other components, functional verification of the target design can be performed. In general, a functional verification system operating in an emulation environment needs to generate output data values quickly such that the output data is available in a timely manner for the other components.
In contrast, in a simulation environment, a designer specifies pre-determined input data and evaluates the target design against the input data. The output data generated by the evaluation is examined to determine whether the design performs the desired functions. Once a designer is satisfied with a design, the data representing the design is sent for fabrication as an integrated circuit.
Accuracy in the functional verification is an important requirement in the design process for several reasons. For example, it is relatively less expensive to alter a circuit design prior to fabrication compared to re-designing and sending the design data for fabrication. In addition, it may require several weeks of time to redesign and complete fabrication again. Such levels of delays may be unacceptable, particularly in the high-technology markets where short design cycles are generally important.
In addition to accuracy, the verification step needs to scale well to the functional verification of integrated circuits of large sizes. That is, a verification systems needs to provide for verification of integrated circuit designs of large sizes. As is well known, an integrated circuit (semi-conductor chip) can include transistors of the order of a few millions, and the number has been increasing over time.
Furthermore, it is generally desirable that the verification step be completed quickly or with minimal internal computations. The speed of verification is particularly important in view of the increase in size and complexity of integrated circuits. To decrease the total design cycle time, it is desirable that the functional verification be completed quickly.
Co-pending U.S. Patent Application entitled, xe2x80x9cFunctional Verification of Integrated Circuit Designsxe2x80x9d, Ser. No. 09/097,874, Filed: Jun. 15, 1998, describes some functional verification systems in which a target design is partitioned into many combinatorial logic blocks connected by sequential elements (e.g., flip-flops) and with appropriate dependencies. The state tables corresponding to the logic blocks are evaluated and stored in multiple random access storage devices (RASDs).
The output corresponding to each input combination is stored such that the output is retrieved from the corresponding RASD when the input combination is provided as a memory address to the RASD. For example, assuming a four input combinatorial logic and a RASD having four bits address bus, if the output the combinatorial logic is to be a 1 corresponding to an input of 1011, a xe2x80x981xe2x80x99 is stored in the memory location corresponding to address 1011.
Cross-connects (XCONs) may interconnect the RASDs and enforce the dependencies which preserve the overall function of the target design. In general, the XCONs provide the outputs resulting from evaluation as memory addresses to RASDs. An XCON may be connected to multiple RASDs, and the XCON together with the connected RASDs may be referred to as a combinatorial logic output evaluator (CLOE).
In an approach described in the co-pending application noted above, each CLOE is connected to 16 other CLOEs (termed as neighbors). One of these CLOEs acts as a central CLOE to communicate with other groups of 16 CLOEs. In other words, if the output of a combinatorial logic evaluated in a first group and the output is to be provided as an input to a RASD in another group, the central CLOEs of the two groups may need to communicate to enable the necessary data transfer.
Such an approach may have several disadvantages. For example, the scheduling of evaluation of a combinatorial block may be undesirably complicated as the inputs may need to be communicated from several CLOEs and due to the xe2x80x98hierarchyxe2x80x99 in communication resulting from the central CLOE. Accordingly, the embodiments of the co-pending application may not be suitable in some environments.
Therefore, what is needed is a method and apparatus which enables the CLOE outputs to be communicated in an efficient manner such that the evaluations can be scheduled and performed quickly. In addition, the approach generally needs to allows for one or more of several related features such as tracing, verification of cycle based and non-cycle based designs, etc.
The present invention relates to a system in which a target design requiring functional verification is partitioned into multiple combinatorial blocks, with the output of the combinatorial blocks being used as inputs to evaluate additional combinatorial blocks until the verification of the target design is complete. According to an aspect of the present invention, multiple combinatorial blocks are assigned to a combinatorial logic output evaluation (CLOE). The outputs of the evaluations of a CLOE may be required by several other CLOEs.
The outputs of CLOEs may be provided on a bus such that several CLOEs may simultaneously access the output data, and store the data locally. The data may then be used as inputs for several evaluations. Due to the availability of the data locally, the scheduling of later evaluations may be simplified.
A CLOE may contain a cross-connect (XCON) which receives the outputs of evaluations from a previous machine cycles and generates a memory address for a present machine cycle. The memory address is used to access data stored in a random access storage device (RASD), thus evaluating the combinatorial blocks, whose outputs are stored in the accessed RASD location.
Several CLOEs may be driven by a run time control unit (RTC). The run time control unit may receive the outputs of evaluation, and forward the outputs to several CLOEs using a bus. The CLOEs may then selectively store the required bits. To control the sequence of evaluations, the run time control unit may provide a cluster number to all the connected CLOEs. As described in further detail below, a cluster generally refers to a group of combinatorial blocks which are evaluated in parallel and a cluster number is used to uniquely identify each cluster. The combinatorial blocks within a cluster are distributed among different CLOEs, such that the combinatorial blocks in a given cluster can be evaluated in parallel in a single machine cycle.
Each XCON may contain multiple muxkongs, with each muxkong being designed to select and store some of the output bits generated in a previous machine cycle. In one embodiment, an XCON may contain 16 muxkongs. As noted above, several combinatorial blocks within a cluster may be evaluated in parallel by several CLOEs in the same machine cycle, and it may therefore be necessary to select and store in each muxkong many outputs generated in a previous machine cycle.
Accordingly, each muxkong may contain many (e.g., 8) multiplexors and a corresponding number of RAMs. Each multiplexor is designed to select any one of the bits provided on the bus, and to store the selected bit in the corresponding RAM. The specific bit selected and the memory address at which the bit is stored is determined based on the cluster number to which the received bits relate to.
In one embodiment, one or more stacks are programmed to indicate the specific bits to be selected, the addresses at which the selected bits are to be stored, and the stacks are used to drive the multiplexors and the RAMs to select and store the bits. A combinatorial logic output generator may partition a target design into combinatorial blocks, determine the sequence of evaluations based on the dependencies among the combinatorial blocks, and configure the stacks and the run time controller consistent with the determined sequence.
With respect to evaluations, each muxkong may provide a bit of a memory address used to retrieve the output of a RASD location, with the retrieved location representing the output of combinatorial blocks. The read operation from the individual RAMs in the muxkongs may be controlled by the configuration performed by CLOG and the cluster number sent by run time controller. Another multiplexor contained in each muxkong may select one bit as an output if more than one RAM provides a bit.
An evaluation control unit may receive each bit generated by a muxkong, and generate an address for a RASD, further based on the specific cluster number presently under consideration. The cluster number may be used to identify the specific bits representing the evaluation outputs of the specified cluster. The evaluation control unit then sends the identified bits to the run time controller.
The run time controller may receive the evaluated bits from several CLOEs (or more specifically from evaluation control units), and send the outputs on a bus such that the CLOEs requiring any output(s) for future evaluation may select and store the required bits.
In one embodiment, a target design may be partitioned into as many as 16K (214) clusters, such that a cluster identifier may be specified using 14 bits. Each XCON may contain 16 muxkongs, and each muxkong may contain eight dual-ported RAMs, with each RAM containing 2K bits of storage.
Thus, the present invention enables functional verification of target systems to be performed quickly as several combinatorial blocks can be evaluated in a single machine cycle.
The present invention may ensure timely availability of data required for evaluation of combinatorial blocks as the input data may be stored locally in the evaluation units immediately upon the availability of the input data.
The present invention may simplify the scheduling of evaluations as the evaluation outputs are stored locally in evaluation control units.
The present invention enables the sequence of evaluations to be controlled by using a cluster number associated with each group of combinatorial blocks which can be evaluated in parallel, and by using the cluster number to schedule the evaluation of the blocks in each group.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.